1. Technical Field
The disclosure herein relates to a data bus sense amplifier circuit and, more particularly, to a two-stage data bus sense amplifier circuit.
2. Related Art
A conventional semiconductor memory device latches cell data, which corresponds to a word line activated by a row address, through a bit line sense amplifier. Then, when a column address is received, the information of the bit line sense amplifier is amplified again in a data bus sense amplifier. In order to improve the sensing ability of such a data bus sense amplifier, a two-stage sense amplifier is used.
FIG. 1 is a conceptual block diagram of a conventional two-stage data bus sense amplifier circuit. The conventional data bus sense amplifier circuit includes a first sense amplifier block 10, a second sense amplifier block 20 and a delay unit 30.
In the data bus sense amplifier circuit, when a predetermined potential difference exists between the levels of signals sensed in the first sense amplifier block 10, the second sense amplifier block 20 starts sensing operation. That is, inputted bit line signals (BL) and (BLB) are amplified through both the first sense amplifier block 10 and the second sense amplifier block 20 to be provided as output signals (DOUT) and (DOUTB).
More specifically, the bit line signals (BL) and (BLB) are sensed by the first sense amplifier block 10 to be provided as the first amplified signals (OUT) and (OUTB). The first amplified signals (OUT) and (OUTB) are sensed again by the second sense amplifier block 20 to be provided as the output signals (DOUT) and (DOUTB). The output signals (DOUT) and (DOUTB) are provided to a global data line.
Meanwhile, the delay unit 30 provides first and second enable signals (S1) and (S2) to the first sense amplifier block 10 and the second sense amplifier block 20, respectively. Although the first and second enable signals (S1) and (S2) respond to a column control pulse signal (Y_pulse), they can have different activation timings with different delay amounts. Nevertheless, they have the same pulse width as the column control pulse signal (Y_pulse). Thus, a section in which the first enable signal (S1) is activated can overlap with a section in which the second enable signal (S2) is activated. Since the first sense amplifier block 10 can operate even during the sensing operation of the second sense amplifier block 20, the current consumption can be increased.